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Pull requests: llvm/circt
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[ImportVerilog] Remove unnecessary field
ModuleLowering::canonicalBody
#10473
opened May 15, 2026 by
rocallahan
Contributor
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[circt-verilog] Add bytecode emission
#10472
opened May 14, 2026 by
fabianschuiki
Contributor
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[circt-synth] Transform Dialect support Pr 1
#10471
opened May 14, 2026 by
markram1729
Contributor
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[Sim] Improve cleanup logic in ProceduralizeSim
#10469
opened May 14, 2026 by
fzi-hielscher
Contributor
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[ImportVerilog] Preserve declaration order across regular and interface-modport ports
#10468
opened May 14, 2026 by
micprog
Contributor
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ci: declare minimum permissions on dispatchCirctTests workflow
#10462
opened May 14, 2026 by
arpitjain099
Contributor
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[LowerToHW] Add support for lower-to-core in firrtl.fprintf
#10452
opened May 13, 2026 by
nanjo712
Contributor
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[LowerToHW] Emit sim.proc.print nested in sim.triggered instead of sim.print
#10451
opened May 13, 2026 by
nanjo712
Contributor
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[Sim] Extract common logic of ProceduralizeSim for reuse
#10422
opened May 9, 2026 by
nanjo712
Contributor
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[FIRRTL] Add mux2cell/mux4cell canonicalization patterns
#10414
opened May 8, 2026 by
anaumchev
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[debug][firrtl] Carry Chisel source-level types through the pipeline
#10410
opened May 7, 2026 by
fkhaidari
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[HW] HWVectorization Part 4: Partial Vectorization (Chunking)
#10399
opened May 6, 2026 by
mafeguimaraes
Contributor
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[ImportVerilog] Support use-before-declare across module bodies
#10350
opened Apr 28, 2026 by
AmurG
Contributor
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[FIRRTL] LowerLayers: Inline enabled layers
FIRRTL
Involving the `firrtl` dialect
#10348
opened Apr 28, 2026 by
rwy7
Contributor
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[ImportVerilog]
HierarchicalNames should skip reprocessing identical module instances
#10341
opened Apr 28, 2026 by
rocallahan
Contributor
•
Draft
fix: update flattenIndices to generate correct indices for a flattened memref
#10327
opened Apr 25, 2026 by
Abhilekhgautam
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