[ImportVerilog] Preserve declaration order across regular and interface-modport ports

[micprog]

When a module's port list interleaves an interface-modport port with regular outputs, the instance-port plumbing produced moore.instance / moore.output verifier failures of the form operand N (...) does not match input/output type (...) of module @M.

convertModuleHeader walked the AST port list in order and pushed each port (regular or expanded interface-modport) to modulePorts interleaved by declaration order. But convertModuleBody built the moore.output operand vector by walking lowering.ports first (regular outputs only) and then lowering.ifacePorts (interface outputs only), and the visit-instance code did the same for the moore.instance operand and result vectors. Whenever the declaration order had an interface-modport output before a regular output, the operand vector and the module signature were permutations of each other and verification fired.

Fix: record an output slot index (outputIdx) on PortLowering and FlattenedIfacePort at header time, and a matching input slot index (inputIdx). Track numExplicitOutputs / numExplicitInputs on ModuleLowering. Build outputs / inputValues / outputValues as fixed-size vectors and place values by slot index, both at the module's terminator and at the instance call site. Hierarchical-name ports keep their existing append-after-explicit-ports treatment.

Regression test: interface-port-order.sv exercises a declaration order with an interface-modport output (l32) before a regular output (l64). The widths differ so any swap trips the moore.output terminator's verifier (the terminator is rigid, with no materializeConversion between operands and declared port types).

Assisted-by: Claude Code:claude-opus-4-7

[circt-bot]

Results of circt-tests run for da1902c compared to results for 537b162:

sv-tests

Changes in emitted diagnostics:

• 0 total change
• -1 error: unknown hierarchical name `P`
• +1 error: unsupported port