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[SimToSV][HWToSV] Print-like SV operations are not guarded from synthesis

Status: Open.

#10489 In llvm/circt;

· nanjo712 opened on May 16, 2026

[Synth] Add an operation for declarative Cut rewrite pattern

Status: Open.

#10485 In llvm/circt;

· uenoku opened on May 16, 2026

[Synth][FunctionalReduction] Fold constants

good first issueGood for newcomersGood for newcomers

Synth

Status: Open.

#10484 In llvm/circt;

· uenoku opened on May 16, 2026

[FIRRTL] Get -fixup-eicg-wrapper working with domains

bugSomething isn't workingSomething isn't working

FIRRTLInvolving the `firrtl` dialectInvolving the `firrtl` dialect

Status: Open.

#10482 In llvm/circt;

· seldridge opened on May 16, 2026

Feature request: add UDP support

Status: Open.

#10477 In llvm/circt;

· rhanqtl opened on May 15, 2026

[Synth] Enhance 3-input logic operations

Status: Open.

#10407 In llvm/circt;

· uenoku opened on May 7, 2026

[FIRRTL][InferResets] Disallow external modules on InstanceChoice?

Status: Open.

#10406 In llvm/circt;

· uenoku opened on May 7, 2026

[Synth] Add attribute for linear delay model and pass to approximate them from NLDM attr

Status: Open.

#10382 In llvm/circt;

· uenoku opened on May 5, 2026

[Seq] FIFO lowering: emits unguarded assert property, breaking synthesis

SeqInvolving the `seq` dialectInvolving the `seq` dialect

verif

Status: Open.

#10378 In llvm/circt;

· teqdruid opened on May 4, 2026

[ExportVerilog] Add option to limit identifier length

ExportVerilog

Status: Open.

#10356 In llvm/circt;

· teqdruid opened on Apr 29, 2026

Feature Request: Native support for negedge clock in FIRRTL

Status: Open.

#10329 In llvm/circt;

· sequencer opened on Apr 26, 2026

[--flatten-memref] Flattened Indices are incorrect

Status: Open.

#10326 In llvm/circt;

· Abhilekhgautam opened on Apr 25, 2026