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Nightly integration tests Nightly integration tests #2210: Scheduled
In progress main
main
In progress
Dispatch circt-tests Dispatch circt-tests #59: completed by AmurG
9s
9s
[ImportVerilog] Support use-before-declare across module bodies Build and Test #37358: Pull request #10350 synchronize by AmurG
16m 13s AmurG:amurg/uvm-pr3-importverilog-testbench-compat
AmurG:amurg/uvm-pr3-importverilog-testbench-compat
16m 13s
[Draft][Moore][ImportVerilog][MooreToCore][Sim] Add file I/O system tasks support. Build and Test #37357: Pull request #10460 synchronize by VecoMr
Action required VecoMr:moore-ibex-support-fopen-fclose
VecoMr:moore-ibex-support-fopen-fclose
Action required
Dispatch circt-tests Dispatch circt-tests #58: completed by nanjo712
13s
13s
[SimToSV] Use SparseOpSCC for cleanup Build and Test #37356: Pull request #10476 synchronize by nanjo712
17m 45s nanjo712:refactor/new-cleanup-logic-for-sim-to-sv
nanjo712:refactor/new-cleanup-logic-for-sim-to-sv
17m 45s
Dispatch circt-tests Dispatch circt-tests #57: completed by nanjo712
1s
1s
[SimToSV] Use SparseOpSCC for cleanup Build and Test #37355: Pull request #10476 opened by nanjo712
38s nanjo712:refactor/new-cleanup-logic-for-sim-to-sv
nanjo712:refactor/new-cleanup-logic-for-sim-to-sv
38s
Dispatch circt-tests Dispatch circt-tests #56: completed by nanjo712
10s
10s
[LowerToHW] Add support for lower-to-core in firrtl.fprintf Build and Test #37354: Pull request #10452 synchronize by nanjo712
16m 41s nanjo712:feat/lower-firrtl-fprint-to-sim
nanjo712:feat/lower-firrtl-fprint-to-sim
16m 41s
Dispatch circt-tests Dispatch circt-tests #55: completed by nanjo712
9s
9s
[LowerToHW] Add support for lower-to-core in firrtl.fprintf Build and Test #37353: Pull request #10452 synchronize by nanjo712
16m 50s nanjo712:feat/lower-firrtl-fprint-to-sim
nanjo712:feat/lower-firrtl-fprint-to-sim
16m 50s
Dispatch circt-tests Dispatch circt-tests #54: completed by nanjo712
18s
18s
[LowerToHW] Add support for lower-to-core in firrtl.fprintf Build and Test #37352: Pull request #10452 synchronize by nanjo712
10m 16s nanjo712:feat/lower-firrtl-fprint-to-sim
nanjo712:feat/lower-firrtl-fprint-to-sim
10m 16s
Upload Release Artifacts Upload Release Artifacts #1270: Scheduled
2h 59m 46s main
main
2h 59m 46s
Dispatch circt-tests Dispatch circt-tests #53: completed by nanjo712
21m 19s
21m 19s
[Sim] Set the GetFileOp operation to procedural only Build and Test #37351: Pull request #10474 synchronize by nanjo712
23m 50s nanjo712:refactor/make-getfileOp-proceduralOp
nanjo712:refactor/make-getfileOp-proceduralOp
23m 50s
Dispatch circt-tests Dispatch circt-tests #52: completed by AmurG
14s
14s
[ImportVerilog] Support use-before-declare across module bodies Build and Test #37350: Pull request #10350 synchronize by AmurG
17m 20s AmurG:amurg/uvm-pr3-importverilog-testbench-compat
AmurG:amurg/uvm-pr3-importverilog-testbench-compat
17m 20s
Dispatch circt-tests Dispatch circt-tests #51: completed by uenoku
9s
9s
Dispatch circt-tests Dispatch circt-tests #50: completed by uenoku
10s
10s
[LowerToHW] Emit sim.proc.print nested in sim.triggered instead of si… Build and Test #37349: Commit 7ffa508 pushed by uenoku
17m 20s main
main
17m 20s
[circt-synth] Transform Dialect support PR 1 (#10471) Build and Test #37348: Commit 1a84614 pushed by uenoku
16m 15s main
main
16m 15s
Dispatch circt-tests Dispatch circt-tests #49: completed by okekayode
9s
9s
[Synth] add onehot gate Build and Test #37347: Pull request #10475 synchronize by okekayode
17m 30s okekayode:dev/synth-onehot
okekayode:dev/synth-onehot
17m 30s