[Sim] Extract common logic of ProceduralizeSim for reuse#10422
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I think it's ready for review now! 🚀 |
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Thanks, @nanjo712. My impression is that we should not be embedding the ProceduralizeSim logic into other passes and instead should begin phasing out both ProceduralizeSim and the non-procedural versions of the sim operations. My suggestion would be to add a %msg = sim.fmt.literal "foo"
sim.print %msg on %clk if %condcould be substituted by %msg = sim.fmt.literal "foo"
sim.triggered %clock if %cond {
sim.proc.print %msg
}And then let the FIRRTL frontend directly build the I've also just merged the "SparseOpSCC" utility: #10305 This might come in handy in situations where we need to manipulate subgraphs of sim operations. |
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Thanks for feedback, @fzi-hielscher .The reason I'm implementing it this way is that FIRRTL itself doesn't contain a procedural print operation (only firrtl.print, similar to sim.print). Some proceduralization step is still needed to create a procedural container in the FIRRTL->Sim flow. Therefore, I've relaxed the input Ops allowed by ProceduralizeSim to directly convert from firrtl.print to sim.proc.print in #10441, thus bypassing the need for sim.print. I think sim.triggered is a good suggestion; as a procedural container specifically for simulation operations, I believe it would be better than using hw.triggered. However, I have some questions about adding an optional conditional operand: As I understand it, if there are two print operations with the same clock but different conditions, in such a design, this might be split into two different sim.print %msg1 on %clk if %cond1 // or some ops like firrtl.print
sim.print %msg2 on %clk if %cond2This would become: sim.triggered %clk if %cond1 {
sim.proc.print %msg1
}
sim.triggered %clk if %cond2 {
sim.proc.print %msg2
}This seems to make the execution order of these two operations very ambiguous. Would it be better to use sim.triggered as an event-scoped region per clock, and keep the individual print conditions inside the region? For example: sim.triggered %clk {
scf.if %cond1 {
sim.proc.print %msg1
}
scf.if %cond2 {
sim.proc.print %msg2
}
} |
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I think I may still be missing part of the intended benefit of If the goal is to avoid the pattern of: then I am not sure that introducing Because of that, it seems that some part of the FIRRTL-to-Sim lowering still has to perform a similar transformation from this non-procedural, event-qualified operation into a procedural/event-scoped representation. Maybe the intended distinction is that FIRRTL lowering would build |
I'd like to keep the FIRRTL to Sim lowering as simple as possible. The primary benefit of lowering directly to
True. The order of side-effects between FIRRTL operations is a different a story. FIRRTL doesn't really provide a solid specification here. The question is whether we want to establish a defined order during FIRRTL lowering despite that and how much effort we put into it. I cannot provide an authoritative answer for that question. But my suggestion would be to keep it simple and aligned with the current SV lowering, which does not establish an order. We can discuss if and how we should refine this later. By running ProceduralizeSim shortly after LowerToHW, and letting it squash all Whether I tried a "big bang" solution to all of this a year and a half ago. It didn't work out too well. 😉 |
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This is indeed a complex issue. I agree with your point: let's start with some incremental changes, at least to avoid making the changes too drastic. Let's begin by introducing a |
Assisted-by: Codex: GPT-5.4
Extract common logic of ProceduralizeSim for reuse.