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[doc] Add documentation about layer-under-layer errors and how to mitigate

Status: Open.

#5244 In chipsalliance/chisel;

· seldridge opened on Mar 25, 2026

SRAM.masked broken when the mask is a constant of all 1s

Status: Open.

#5243 In chipsalliance/chisel;

· elipsitz opened on Mar 24, 2026

suffix always be "sv"

Status: Open.

#5231 In chipsalliance/chisel;

· balanx opened on Mar 14, 2026

ChiselSim cannot deal with 0-width signals and DontCare values

Status: Open.

#5230 In chipsalliance/chisel;

· ccromjongh opened on Mar 13, 2026

Escape FIRRTL Keywords in Emission

Status: Open.

#5218 In chipsalliance/chisel;

· seldridge opened on Feb 27, 2026

Boring from a Probe with U-turn can cause illegal FIRRTL

bug

Status: Open.

#5130 In chipsalliance/chisel;

· seldridge opened on Dec 20, 2025

how to annotations to ltl properties

Status: Open.

#5118 In chipsalliance/chisel;

· doofin opened on Dec 12, 2025

chisel3.cover drops label in FIRRTL emission

bug

Status: Open.

#5114 In chipsalliance/chisel;

· seldridge opened on Dec 9, 2025

Line up poke() and register output changes in .vcd trace

Status: Open.

#5107 In chipsalliance/chisel;

· oharboe opened on Dec 5, 2025

Chisel 8 Tracker

Status: Open.

#5100 In chipsalliance/chisel;

· seldridge opened on Nov 27, 2025

Adding custom information to Chisel for CIRCT Passes

Status: Open.

#5078 In chipsalliance/chisel;

· liuyic00 opened on Nov 24, 2025

[chiselsim] stepUntil, but asserting if it doesn't happen?

Status: Open.

#5077 In chipsalliance/chisel;

· seldridge opened on Nov 22, 2025