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    44 repositories

    • eecs150.github.io

      Public
      Website for Sp24 hosted on Github Pages
      Verilog
      •0•5•0•0•Updated Jan 17, 2025Jan 17, 2025

    • fpga_project_skeleton_fa22

      Public
      Verilog
      •
      BSD 3-Clause "New" or "Revised" License
      •8•19•0•0•Updated Aug 1, 2024Aug 1, 2024

    • asic-project-sp24

      Public
      C
      •3•7•0•0•Updated Apr 27, 2024Apr 27, 2024

    • fpga_project_sp24

      Public
      Verilog
      •2•3•0•0•Updated Apr 23, 2024Apr 23, 2024

    • asic-labs-sp24

      Public template
      Labs for Spring 2024 semester
      Verilog
      •21•5•0•0•Updated Mar 6, 2024Mar 6, 2024

    • fpga_labs_sp24

      Public
      Verilog
      •7•7•0•0•Updated Mar 4, 2024Mar 4, 2024

    • simple-office-hours-queue

      Public
      Simple Office Hours Queue (SOHQ) is an open source online queue where students can request help and staff members can manage their office hours.
      TypeScript
      •8•0•0•0•Updated Feb 19, 2024Feb 19, 2024

    • asic_labs

      Public
      Verilog
      •2•2•0•0•Updated Sep 14, 2023Sep 14, 2023

    • asic-labs-sp23

      Public
      Lab specs for asic-labs-sp23 is organized here!
      6•10•0•0•Updated May 5, 2023May 5, 2023

    • fpga_project_sp23

      Public
      Verilog
      •1•3•0•0•Updated Apr 29, 2023Apr 29, 2023

    • website_f22

      Public
      HTML
      •1•1•0•0•Updated Feb 9, 2023Feb 9, 2023

    • asic-labs-fa22

      Public
      18•20•1•0•Updated Dec 11, 2022Dec 11, 2022

    • fpga_labs_fa22

      Public
      Verilog
      •29•24•0•0•Updated Oct 18, 2022Oct 18, 2022

    • project_skeleton_sp22

      Public
      TeX
      •2•4•0•0•Updated Oct 12, 2022Oct 12, 2022

    • asic_labs_sp22

      Public
      12•29•0•0•Updated Oct 3, 2022Oct 3, 2022

    • website_s22

      Public
      HTML
      •0•2•0•0•Updated May 17, 2022May 17, 2022

    • fpga_labs_sp22

      Public
      Verilog
      •37•36•2•0•Updated Mar 16, 2022Mar 16, 2022

    • project_skeleton_fa21

      Public
      FPGA Project for EECS 151/251A (Fall 2021)
      Verilog
      •19•7•0•0•Updated Jan 10, 2022Jan 10, 2022

    • website_fa21

      Public
      HTML
      •1•1•0•0•Updated Dec 17, 2021Dec 17, 2021

    • asic_labs_fa21

      Public
      28•24•1•0•Updated Dec 8, 2021Dec 8, 2021

    • fpga_labs_fa21

      Public
      FPGA Labs for EECS 151/251A (Fall 2021)
      Verilog
      •25•11•1•0•Updated Oct 20, 2021Oct 20, 2021

    • project_skeleton_sp21

      Public archive
      Verilog
      •5•8•0•0•Updated May 21, 2021May 21, 2021

    • arm_baremetal_app

      Public archive
      C
      •1•0•0•0•Updated Apr 11, 2021Apr 11, 2021

    • fpga_labs_sp21

      Public archive
      TeX
      •5•10•0•0•Updated Mar 2, 2021Mar 2, 2021

    • fpga_project_skeleton_fa20

      Public archive
      Verilog
      •4•3•0•0•Updated Dec 11, 2020Dec 11, 2020

    • fpga_labs_fa20

      Public archive
      FPGA lab skeleton files and specs for EECS 151/251A Fall 2020
      Verilog
      •4•2•0•0•Updated Oct 23, 2020Oct 23, 2020

    • disc_fa19

      Public archive
      Discussion slides/code for EECS 151/251A Fall 2019
      TeX
      •3•1•0•0•Updated Aug 13, 2020Aug 13, 2020

    • project_skeleton_sp20

      Public archive
      EECS 151/251A FPGA Project Skeleton for Spring 2020
      Verilog
      •4•12•0•0•Updated May 6, 2020May 6, 2020

    • fpga_labs_sp20

      Public archive
      FPGA lab skeleton files and specs for EECS 151/251A Spring 2020
      Verilog
      •3•4•0•0•Updated Apr 9, 2020Apr 9, 2020

    • disc_sp20

      Public archive
      0•0•0•0•Updated Jan 23, 2020Jan 23, 2020
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