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Add Pulse Waveform Generator (PWG) for DMA-driven GPIO pulse trains
Timer-triggered DMA writes to GPIO BSRR from a circular double buffer, producing jitter-free pin toggling at configurable frequency. A background thread refills the inactive buffer half via user-supplied callback. Intended for stepper motor control and similar precise pulse applications. STM32H7 support with DMAMUX routing for TIM1-TIM8.
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‎include/mios/pwg.h‎

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/**
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* @file pwg.h
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* @brief Pulse Waveform Generator (PWG)
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*
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* The PWG generates jitter-free pulse trains by using a hardware timer
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* to trigger DMA transfers from a memory buffer to a GPIO port's BSRR
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* (Bit Set/Reset Register). This produces cycle-accurate pin toggling
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* with zero CPU involvement during steady-state operation.
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*
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* A background thread refills the inactive half of a circular
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* double-buffer via a user-supplied callback. At the configured
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* timer frequency, DMA writes one 32-bit word per tick to BSRR:
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*
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* Bits 0-15: Set corresponding GPIO pin high
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* Bits 16-31: Reset corresponding GPIO pin low (bit 16 = pin 0, etc.)
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*
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* Writing 0 to a BSRR word leaves all pins unchanged for that tick.
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*
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* All controlled pins must reside on the same GPIO port. For pins
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* on different ports, create separate PWG instances.
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*
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* Typical use: stepper motor control where STEP and DIR pins on the
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* same port need precisely timed pulse sequences.
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*/
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#pragma once
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#include <stdint.h>
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#include <stddef.h>
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/**
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* Callback invoked by the PWG fill thread whenever a half-buffer
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* needs new data.
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*
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* @param opaque User-supplied context pointer
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* @param buf Pointer to the half-buffer to fill (32 entries)
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* @param count Number of uint32_t entries to write
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*
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* Each entry is a BSRR value that will be written to the GPIO port
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* on successive timer ticks. The callback must fill all 'count'
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* entries before returning.
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*/
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typedef void (*pwg_fill_cb)(void *opaque, uint32_t *buf, size_t count);

‎src/platform/stm32/stm32_pwg.c‎

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// This file is not compiled on its own but needs to be included
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// by a stm32 chip specific file
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#include <mios/pwg.h>
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#include <malloc.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include "cache.h"
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#define PWG_BUF_SIZE 64
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#define PWG_HALF_SIZE (PWG_BUF_SIZE / 2)
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typedef struct stm32_pwg {
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// DMA buffer must be cache-line aligned and not share cache lines
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// with other fields, since we use dcache_op(DCACHE_CLEAN) on it.
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uint32_t buf[PWG_BUF_SIZE];
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uint32_t timer_base;
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uint32_t gpio_bsrr_addr;
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stm32_dma_instance_t dma;
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task_waitable_t waitq;
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pwg_fill_cb fill_cb;
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void *opaque;
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uint8_t active_half;
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uint8_t running;
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} stm32_pwg_t;
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static void
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pwg_dma_cb(stm32_dma_instance_t inst, uint32_t status, void *arg)
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{
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stm32_pwg_t *pwg = arg;
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if(status & DMA_STATUS_HALF_XFER)
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pwg->active_half = 1;
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if(status & DMA_STATUS_FULL_XFER)
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pwg->active_half = 0;
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task_wakeup_sched_locked(&pwg->waitq, 0);
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}
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static void *
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pwg_thread(void *arg)
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{
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stm32_pwg_t *pwg = arg;
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pwg->fill_cb(pwg->opaque, &pwg->buf[0], PWG_HALF_SIZE);
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pwg->fill_cb(pwg->opaque, &pwg->buf[PWG_HALF_SIZE], PWG_HALF_SIZE);
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dcache_op(pwg->buf, sizeof(pwg->buf), DCACHE_CLEAN);
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stm32_dma_start(pwg->dma);
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reg_wr(pwg->timer_base + TIMx_CR1, 1);
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while(pwg->running) {
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int q = irq_forbid(IRQ_LEVEL_SCHED);
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task_sleep_sched_locked(&pwg->waitq);
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uint8_t active = pwg->active_half;
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irq_permit(q);
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uint32_t *half = active ?
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&pwg->buf[0] : &pwg->buf[PWG_HALF_SIZE];
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pwg->fill_cb(pwg->opaque, half, PWG_HALF_SIZE);
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dcache_op(half, PWG_HALF_SIZE * sizeof(uint32_t), DCACHE_CLEAN);
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}
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reg_wr(pwg->timer_base + TIMx_CR1, 0);
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stm32_dma_stop(pwg->dma);
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return NULL;
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}
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static stm32_pwg_t *
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stm32_pwg_init(uint32_t timer_base,
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uint16_t timer_clkid,
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uint32_t dma_resource_id,
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uint32_t gpio_bsrr_addr,
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uint32_t frequency,
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pwg_fill_cb fill_cb,
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void *opaque)
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{
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stm32_pwg_t *pwg = xalloc(sizeof(stm32_pwg_t), CACHE_LINE_SIZE,
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MEM_TYPE_DMA | MEM_CLEAR);
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pwg->timer_base = timer_base;
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pwg->gpio_bsrr_addr = gpio_bsrr_addr;
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pwg->fill_cb = fill_cb;
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pwg->opaque = opaque;
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pwg->running = 1;
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task_waitable_init(&pwg->waitq, "pwg");
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// Configure timer
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clk_enable(timer_clkid);
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uint32_t tclk = clk_get_freq(timer_clkid);
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uint32_t div = tclk / frequency;
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uint32_t psc = 0;
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while(div > 65536) {
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psc++;
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div = tclk / (frequency * (psc + 1));
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}
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reg_wr(timer_base + TIMx_PSC, psc);
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reg_wr(timer_base + TIMx_ARR, div - 1);
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reg_wr(timer_base + TIMx_EGR, 1); // Generate update to load PSC/ARR
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reg_wr(timer_base + TIMx_DIER, 1 << 8); // UDE - Update DMA Enable
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// Configure DMA
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pwg->dma = stm32_dma_alloc(dma_resource_id, "pwg");
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stm32_dma_config(pwg->dma,
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STM32_DMA_BURST_NONE,
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STM32_DMA_BURST_NONE,
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STM32_DMA_PRIO_HIGH,
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STM32_DMA_32BIT,
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STM32_DMA_32BIT,
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STM32_DMA_INCREMENT,
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STM32_DMA_FIXED,
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STM32_DMA_CIRCULAR,
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STM32_DMA_M_TO_P);
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stm32_dma_set_paddr(pwg->dma, gpio_bsrr_addr);
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stm32_dma_set_mem0(pwg->dma, pwg->buf);
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stm32_dma_set_nitems(pwg->dma, PWG_BUF_SIZE);
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stm32_dma_set_callback(pwg->dma, pwg_dma_cb, pwg, IRQ_LEVEL_SCHED,
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DMA_STATUS_HALF_XFER | DMA_STATUS_FULL_XFER);
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thread_create(pwg_thread, pwg, 512, "pwg", TASK_DETACHED, 20);
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return pwg;
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}
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void
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stm32_pwg_stop(stm32_pwg_t *pwg)
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{
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pwg->running = 0;
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task_wakeup(&pwg->waitq, 0);
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}

‎src/platform/stm32h7/stm32h7.mk‎

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${P}/stm32h7_spi.c \
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${P}/stm32h7_adc.c \
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${P}/stm32h7_can.c \
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${P}/stm32h7_pwg.c \
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${P}/stm32h7_systim.c \
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${P}/stm32h7_idle.c \
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${P}/stm32h7_info.c \

‎src/platform/stm32h7/stm32h7_pwg.c‎

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#include <mios/task.h>
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#include <mios/type_macros.h>
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#include "stm32h7_clk.h"
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#include "stm32h7_tim.h"
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#include "stm32h7_dma.h"
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#include "stm32h7_pwg.h"
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#include "irq.h"
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#define GPIO_PORT_ADDR(x) (0x58020000 + ((x) * 0x400))
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#include "platform/stm32/stm32_pwg.c"
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static const struct {
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uint32_t base;
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uint16_t clkid;
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uint8_t dma_resource;
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} pwg_timers[] = {
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[1] = { TIM1_BASE, CLK_TIM1, 15 },
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[2] = { TIM2_BASE, CLK_TIM2, 22 },
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[3] = { TIM3_BASE, CLK_TIM3, 27 },
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[4] = { TIM4_BASE, CLK_TIM4, 32 },
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[5] = { TIM5_BASE, CLK_TIM5, 59 },
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[6] = { TIM6_BASE, CLK_TIM6, 69 },
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[7] = { TIM7_BASE, CLK_TIM7, 70 },
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[8] = { TIM8_BASE, CLK_TIM8, 51 },
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};
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stm32_pwg_t *
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stm32h7_pwg_create(unsigned int timer_instance,
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uint8_t gpio_port,
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uint32_t frequency,
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pwg_fill_cb fill_cb,
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void *opaque)
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{
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if(timer_instance < 1 || timer_instance >= ARRAYSIZE(pwg_timers))
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return NULL;
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return stm32_pwg_init(pwg_timers[timer_instance].base,
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pwg_timers[timer_instance].clkid,
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pwg_timers[timer_instance].dma_resource,
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GPIO_PORT_ADDR(gpio_port) + 0x18,
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frequency,
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fill_cb,
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opaque);
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}

‎src/platform/stm32h7/stm32h7_pwg.h‎

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#pragma once
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#include <mios/pwg.h>
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typedef struct stm32_pwg stm32_pwg_t;
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stm32_pwg_t *stm32h7_pwg_create(unsigned int timer_instance,
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uint8_t gpio_port,
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uint32_t frequency,
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pwg_fill_cb fill_cb,
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void *opaque);
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void stm32_pwg_stop(stm32_pwg_t *pwg);

‎src/platform/stm32h7/stm32h7_tim.h‎

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#pragma once
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#define TIM1_BASE 0x40010000
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#define TIM2_BASE 0x40000000
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#define TIM3_BASE 0x40000400
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#define TIM4_BASE 0x40000800

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