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yuncore-ax835-p5-nand: Enable 2.5G PHY and PHY LEDs
1 parent ea95d50 commit 9c19f6c

1 file changed

Lines changed: 18 additions & 60 deletions

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target/linux/mediatek/dts/mt7981b-yuncore-ax835-p5-nand.dts

Lines changed: 18 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -20,11 +20,6 @@
2020
stdout-path = "serial0:115200n8";
2121
};
2222

23-
//bl2_verify {
24-
// bl2_compatible = "spim-nand";
25-
//};
26-
27-
2823
gpio-keys {
2924
compatible = "gpio-keys";
3025

@@ -74,53 +69,48 @@
7469
led-pattern = <1000>, <1000>;
7570
};
7671

77-
// there's another "syswatchdog" on gpio2
72+
// there's another internal "syswatchdog": &watchdog
7873
};
7974
};
8075
&eth {
8176
status = "okay";
8277
pinctrl-names = "default";
83-
//pinctrl-0 = <&eth_led0>;
78+
pinctrl-0 = <&gbe_led0_pins>;
79+
8480
gmac0: mac@0 {
8581
compatible = "mediatek,eth-mac";
8682
reg = <0>;
8783
phy-mode = "2500base-x";
8884
phy-handle = <&phy5>;
8985
nvmem-cell-names = "mac-address";
9086
nvmem-cells = <&macaddr_factory_2a>;
91-
9287
};
9388

9489
gmac1: mac@1 {
9590
compatible = "mediatek,eth-mac";
9691
reg = <1>;
9792
phy-mode = "gmii";
98-
phy-handle = <&phy0>;
93+
phy-handle = <&int_gbe_phy>;
9994
nvmem-cell-names = "mac-address";
10095
nvmem-cells = <&macaddr_factory_24>;
10196
};
97+
};
10298

103-
mdio: mdio-bus {
104-
#address-cells = <1>;
105-
#size-cells = <0>;
106-
phy0: ethernet-phy@0 {
107-
compatible = "ethernet-phy-id03a2.9461";
108-
reg = <0>;
109-
phy-mode = "gmii";
110-
nvmem-cells = <&phy_calibration>;
111-
nvmem-cell-names = "phy-cal-data";
112-
};
113-
phy5: phy@5 {
114-
compatible = "ethernet-phy-id67c9.de0a";
115-
reg = <5>;
116-
reset-gpios = <&pio 39 1>;
117-
reset-assert-us = <600>;
118-
reset-deassert-us = <20000>;
119-
phy-mode = "2500base-x";
120-
label = "wan";
121-
};
99+
&mdio_bus {
100+
phy5: phy@5 {
101+
compatible = "ethernet-phy-ieee802.3-c45";
102+
reg = <5>;
103+
phy-mode = "2500base-x";
104+
reset-gpios = <&pio 39 1>;
105+
reset-assert-us = <600>;
106+
reset-deassert-us = <20000>;
107+
108+
// configures the led registers
109+
// see VSPEC1_LEDx registers in gpy211 manual
110+
mxl,led-config = <0x00f0 0x0 0x0 0x0>;
122111
};
123112
};
113+
124114
&pio {
125115
spi0_flash_pins: spi0-pins {
126116
mux {
@@ -140,25 +130,6 @@
140130
};
141131

142132
};
143-
144-
spi2_flash_pins: spi2-pins {
145-
mux {
146-
function = "spi";
147-
groups = "spi2", "spi2_wp_hold";
148-
};
149-
150-
conf-pu {
151-
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
152-
drive-strength = <8>;
153-
bias-pull-up = <103>;
154-
};
155-
156-
conf-pd {
157-
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
158-
drive-strength = <8>;
159-
bias-pull-down = <103>;
160-
};
161-
};
162133
};
163134

164135
&spi0 {
@@ -233,23 +204,10 @@
233204
label = "ubi";
234205
reg = <0x580000 0x4000000>;
235206
};
236-
partition@4580000 {
237-
compatible = "linux,ubi";
238-
label = "horst";
239-
reg = <0x4580000 0x3800000>;
240-
};
241207
};
242208
};
243209
};
244210

245-
&spi2 {
246-
pinctrl-names = "default";
247-
pinctrl-0 = <&spi2_flash_pins>;
248-
status = "disabled";
249-
250-
};
251-
252-
253211
&uart0 {
254212
status = "okay";
255213
};

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